The article offers the analysis of operational amplifier parameter changes, when circuits are scaled from 0.18 μm to 65 nm CMOS technology. Two two-stage operational amplifiers were designed for this purpose: first uses n-MOS input differential pair; second uses cascaded active loads structure and p-MOS type input differential pair. The operational amplifiers were designed in 0.18 μm CMOS technology and scaled to 65 nm CMOS. Other scaling methods were also analysed when redesigning circuits from one IC technology to another. Results of the original and scaled operational amplifier parameters are presented and analysed.

Article in Lithuanian