In the article the architecture of a charge pump phase locked loop is shown. The influence on overall system performance of its functional blocks is discussed. Voltage controlled oscillator phase noise analysis is done and the relationship between a charge pump phase locked loop and voltage controlled oscillator phase noises are determined. The requirements and results of the accomplished design are discussed. Area of chip PLL – 150×250 μm², power consumption – 10 mW and phase noise is –125 dBc/Hz with 1 MHz deviation from central 670 MHz frequency.

Article in Lithuanian