Science – Future of Lithuania / Mokslas – Lietuvos Ateitis, Vol 5, No 2 (2013)

Modified SURF Algorithm Implementation on FPGA For Real-Time Object Tracking

Tomyslav Sledevič


The paper describes the FPGA-based implementation of the modified speeded-up robust features (SURF) algorithm. FPGA was selected for parallel process implementation using VHDL to ensure features extraction in real-time. A sliding 84×84 size window was used to store integral pixels and accelerate Hessian determinant calculation, orientation assignment and descriptor estimation. The local extreme searching was used to find point of interest in 8 scales. The simplified descriptor and orientation vector were calculated in parallel in 6 scales. The algorithm was investigated by tracking marker and drawing a plane or cube. All parts of algorithm worked on 25 MHz clock. The video stream was generated using 60 fps and 640×480 pixel camera.

Article in Lithuanian

Article in: Lithuanian

Article published: 2013-05-24

Keyword(s): field programmable gate array; features extraction; video filtering; object tracking

DOI: 10.3846/mla.2013.12

Full Text: PDF pdf

Science – Future of Lithuania / Mokslas – Lietuvos Ateitis ISSN 2029-2341, eISSN 2029-2252
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