The research examined the use of field programmable gate arrays (FPGA) in image filtering. Experimental and theoretical researches were reviewed. Experiments with Cyclone III family FPGA chip with implemented NIOS II soft processor were considered. Image filtering was achieved with symmetrical and asymmetrical finite impulse response filters with convolution kernel. The system, which was implemented with 3×3 symmetrical filter, which was implemented using the hardware description language, uses 59% of logic elements of the chip and 10 multiplication elements. The system with asymmetrical filter uses the same amount of logic elements and 13 multiplication elements. Both filter systems consume approx. 545 mW of power. The system, which is designed for filter implementation in C language, uses 65% of all logical elements and consumes 729 mW of power.

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