Science – Future of Lithuania / Mokslas – Lietuvos Ateitis, Vol 5, No 2 (2013)

FPGA-Based Implementation of Lithuanian Isolated Word Recognition Algorithm

Tomyslav Sledevič
Liudas Stašionis


The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock.

Article in Lithuanian

Article in: Lithuanian

Article published: 2013-05-24

Keyword(s): field programmable gate array; word recognition; cepstrum; dynamic time warping

DOI: 10.3846/mla.2013.18

Full Text: PDF pdf

Science – Future of Lithuania / Mokslas – Lietuvos Ateitis ISSN 2029-2341, eISSN 2029-2252
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 License.