The place of interpolator in ΣΔ DACs was briefly discussed. The summarized structure of the most common interpolators was provided. The more applicable interpolators’ structures were suggested and analyzed in comparison with similar one. Having changed the structure of incomplete interpolator and having optimized the stages, it was possible to improve the characteristic of amplitude transfer by 17 dB with less non-zero coefficients and much less FPGA resources. After experimental research of the full converter system (interpolator, modulator and output filter) it was defined that the designed interpolator (including 17 dB gaining) suits only a very limited set of modulators. Another version of interpolator was offered for the system, ensuring the suppression of the additional frequency band in the whole system above 99 dB instead of the previous 66 dB (or 49 dB in the similar version of interpolator).

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