Science – Future of Lithuania / Mokslas – Lietuvos Ateitis, Vol 6, No 2 (2014)

Design Of A 65 Nm Cmos Comparator With Hysteresis

Aleksandr Vasjanov (Vilniaus Gedimino technikos universitetas, Lithuania)
Vaidotas Barzdėnas (Vilniaus Gedimino technikos universitetas, Lithuania)


The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually operate in conditions, where useful and unwanted (noise) signals are present at the same time. In order to maintain the validity of output data, a hysteresis parameter is introduced to the comparator’s circuit. This article presents the results of a CMOS comparator with hysteresis design – the schematic, topology and simulation results are analyzed. The designed comparator is implemented in a zero voltage offset compensation circuit ADC in a multi-standard transceiver IC.

Article in: English

Article published: 2014-04-24

Keyword(s): CMOS, comparator, hysteresis, integrated circuit, IC, design, chip, ADC.

DOI: 10.3846/mla.2014.30

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Science – Future of Lithuania / Mokslas – Lietuvos Ateitis ISSN 2029-2341, eISSN 2029-2252
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 License.